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I2C-Compatible, Wide Bandwidth, Five 2:1 Multiplexer ADG795A/ADG795G
FEATURES
Bandwidth: 325 MHz Low insertion loss and on resistance: 2.6 typical On resistance flatness: 0.3 typical Single 3 V/5 V supply operation 3.3 V analog signal range (5 V supply, 75 load) Low quiescent supply current: 1 nA typical Fast switching times: tON = 186 ns, tOFF = 177 ns ESD protection 4 kV human body model (HBM) 200 V machine model (MM) 1 kV field-induced charged device model (FICDM) I2C(R)-compatible interface Compact 24-lead LFCSP
FUNCTIONAL BLOCK DIAGRAMS
VDD GND VDD GND
ADG795A
S1A D1 S1B S2A D2 S2B S3A D3 S3B S4A D4 S4B S5A D5 S5B I2C SERIAL INTERFACE S4B S5A S3B S4A S2B S3A S1B S2A S1A
ADG795G
D1
D2
D3
D4
D5 S5B I2C SERIAL INTERFACE GPO1
06034-001
APPLICATIONS
S-Video RGB/YPbPr video switches HDTV Projection TV DVD-R/RW AV receivers
A0
A1
A2 SDA SCL
A0
A1
A2 SDA SCL
Figure 1.
GENERAL DESCRIPTION
The ADG795A/ADG795G are monolithic CMOS devices comprising five 2:1 multiplexers/demultiplexers controllable via a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet gives high switching speed and low on resistance. The on-resistance profile is very flat over the full analog input range and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range make the ADG795A/ADG795G the ideal switching solution for a wide range of TV applications including S-video, RGB and YPbPr video switches. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The ADG795A/ADG795G switches exhibit break-before-make switching action. The ADG795G has one general-purpose logic output pins controlled by the I2C interface that can also be used to control other non-I2C-compatible devices such as video filters. The integrated I2C interface provides a large degree of flexibility in the system design. It has three configurable I2C address pins that allow up to eight devices on the same bus. This allows the user to expand the capability of the device by increasing the size of the switching array. The ADG795A/ADG795G operate from a single 3 V or 5 V supply voltage and are available in a compact 4 mm x 4 mm body, 24-lead, lead-free package (LFCSP).
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. Wide bandwidth: 325 MHz. Ultralow power dissipation. Extended input signal range. Integrated I2C serial interface. Compact 4 mm x 4 mm, 24-lead, lead-free LFCSP. ESD protection tested as per ESD Association standards: 4 kV HBM (ANSI/ESD STM5.1-2001) 200 V MM (ANSI/ESD STM5.2-1999) 1 kV FICDM (ANSI/ESDSTM5.3.1-1999)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADG795A/ADG795G TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Specifications..................................................................................... 3 I2C Timing Specifications ................................................................ 7 Timing Diagram ........................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Test Circuits..................................................................................... 14 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 I2C Serial Interface ..................................................................... 17 I2C Address.................................................................................. 17 Write Operation.......................................................................... 17 LDSW bit..................................................................................... 19 Power On/Software Reset.......................................................... 19 Read Operation........................................................................... 19 Evaluation Board ............................................................................ 20 Using the ADG795G Evaluation Board .................................. 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
7/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADG795A/ADG795G SPECIFICATIONS
VDD = 5 V 10%, GND = 0 V, TA = -40C to +85C, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On-Resistance Matching Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD I2C-to-GPO Propagation Delay, tH, tL Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer -3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS3 A0, A1, A2 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN SCL, SDA Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN Conditions VS = VDD, RL = 1 M VS = VDD, RL = 75 VD = 0 V, IDS = -10 mA, see Figure 22 VD = 0 V to 1 V, IDS = -10 mA, see Figure 22 VD = 0 V, IDS = -10 mA VD = 1 V, IDS = -10 mA VD = 0 V to 1 V, IDS = -10 mA VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 VD = VS = 4 V/1 V, see Figure 24 CL = 35 pF, RL = 50 , VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 , VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 , VS1 = VS2 = 2 V, see Figure 29 ADG795G only f = 10 MHz, RL = 50 , see Figure 26 f = 10 MHz, RL = 50 , see Figure 27 Min 0 0 2.2 0.15 Typ 1 Max 4 3.3 3.5 4 0.5 0.6 0.55 Unit V V nA nA nA 250 240 ns ns ns ns dB dB dB MHz % pC pF pF pF dB % Degrees
0.3 0.25 0.25 0.25 186 177 3
1
130 -60 -55 -70 325 0.14 5 10 13 27 70 0.32 0.44
RL = 50 , see Figure 25 RL = 100 CL = 1 nF, VS = 0 V, see Figure 30
f = 20 kHz CCIR330 test signal CCIR330 test signal
2.0 VIN = 0 V to VDD 0.005 3 0.7 x VDD -0.3 VIN = 0 V to VDD 0.005 0.05 x VDD 3 0.8 1
V V A pF V V A V pF
VDD + 0.3 +0.3 x VDD 1
Rev. 0 | Page 3 of 24
ADG795A/ADG795G
Parameter LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance GPO1 Pin and GPO2 Pin Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS IDD Conditions Min Typ 1 Max Unit
ISINK = 3 mA ISINK = 6 mA
0.4 0.6 1 10 0.4 2.0 0.001 1 0.2 0.7
V V A pF V V A mA mA
ILOAD = +2 mA ILOAD = -2 mA Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL =400 kHz I2C interface active, fSCL =3.4 MHz
1 2 3
All typical values are at TA = 25C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 24
ADG795A/ADG795G
VDD = 3 V 10%, GND = 0 V, TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On-Resistance Matching Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD I2C-to-GPO Propagation Delay, tH, tL Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer -3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS3 A0, A1, A2 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN SCL, SDA Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN Conditions VS=VDD, RL=1M VS=VDD, RL=75 VD = 0 V, IDS = -10 mA, see Figure 22 VD = 0 V to 1 V, IDS = -10 mA, see Figure 22 VD = 0 V, IDS = -10 mA VD = 1 V, IDS = -10 mA VD = 0 V to 1 V, IDS = -10 mA VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23 VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23 VD = VS = 2 V/1 V, see Figure 24 CL = 35 pF, RL = 50 , VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 , VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 , VS1 = VS2 = 2 V, see Figure 29 ADG795G only f = 10 MHz, RL = 50 , see Figure 26 f = 10 MHz, RL = 50 , see Figure 27 Min 0 0 2.2 0.15 Typ 1 Max 2.2 1.7 4 6 0.6 1.1 2.8 Unit V V nA nA nA 270 260 121 -60 -55 -70 310 0.14 2.5 10 13 27 70 0.28 0.28 ns ns ns ns dB dB dB MHz % pC pF pF pF dB % Degree s
0.3 0.25 0.25 0.25 198 195 3
1
RL = 50 , see Figure 25 RL = 100 CL = 1 nF, VS = 0 V, see Figure 30
f = 20 kHz CCIR330 test signal CCIR330 test signal
2.0 VIN = 0 V to VDD 0.005 3 0.7 x VDD -0.3 VIN = 0 V to VDD 0.005 0.05 x VDD 3 0.8 1
V V A pF V V A V pF
VDD + 0.3 +0.3 x VDD 1
Rev. 0 | Page 5 of 24
ADG795A/ADG795G
Parameter LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Floating-State leakage Current Floating-State Output Capacitance GPO1 Pin and GPO2 Pin Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS IDD Conditions Min Typ 1 Max Unit
ISINK = 3 mA ISINK = 6 mA 3
0.4 0.6 1
V V A pF
ILOAD = +2 mA ILOAD = -2 mA Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400 kHz I2C interface active, fSCL = 3.4 MHz
0.4 2.0 0.001 1 0.1 0.2
V V A mA mA
1 2 3
All typical values are at TA = 25C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 24
ADG795A/ADG795G I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; GND = 0 V; TA = -40C to +85C, unless otherwise noted. See Figure 2 for timing diagram. Table 3.
Parameter 1 fSCL Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 0 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 Unit kHz kHz MHz MHz s s ns ns s s ns ns ns ns ns s s ns ns s s ns s s ns s s s s ns ns ns ns ns ns ns ns ns Description Serial clock frequency
t1
tHIGH, SCL high time
t2
tLOW, SCL low time
t3
tSU;DAT, data setup time
t4 2
3.45 0.9 703 150
tHD;DAT, data hold time
t5
tSU;STA, setup time for a repeated start condition
t6
tHD;STA, hold time (repeated) start condition
t7 t8
tBUF, bus free time between a stop and a start condition tSU;STO, setup time for stop condition
t9
1000 300 80 160 300 300 80 160
tRDA, rise time of SDA signal
t10
tFDA, fall time of SDA signal
Rev. 0 | Page 7 of 24
ADG795A/ADG795G
Parameter 1 t11 Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Fast mode High speed mode Min 20 + 0.1 CB 10 20 Max 1000 300 40 80 1000 300 80 160 300 300 40 80 50 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description tRCL, rise time of SCL signal
t11A
tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 0 0
t12
tFCL, fall time of SCL signal
tSP
Pulse width of suppressed spike
1
2
Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD. A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
t11
SCL
t12
t2 t6 t4 t1 t3 t5 t10
t6
t8 t9
06034-002
SDA
t7
P S S P
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 24
ADG795A/ADG795G ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameters VDD to GND Analog, Digital Inputs Continuous Current, S or D Peak Current, S or D Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance 24-Lead LFCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Ratings -0.3 V to +6 V -0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA 300 mA (pulsed at 1 ms, 10% duty cycle max) -40C to +85C -65C to +150C 150C 30C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 9 of 24
ADG795A/ADG795G PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND VDD SDA SCL A0 A1 GND VDD SDA SCL A0 A1
18 17 16 15 14 13 A2 NC NC D5 S5B S5A S1A S1B D1 D2 S2B S2A 1 2 3 4 5 6
24 23 22 21 20 19
S1A S1B D1 D2 S2B S2A
1 2 3 4 5 6
PIN 1 INDICATOR
24 23 22 21 20 19
PIN 1 INDICATOR
TOP VIEW (Not to Scale)
ADG795A
TOP VIEW (Not to Scale)
ADG795G
18 17 16 15 14 13
A2 NC GPO1 D5 S5B S5A
7 8 9 10 11 12
S3A S3B D3 D4 S4B S4A
06034-004
Figure 3. ADG795G Pinout
Figure 4. ADG795A Pinout
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic S1A S1B D1 D2 S2B S2A S3A S3B D3 D4 S4B S4A S5A S5B D5 NC/GPO1 NC A2 A1 A0 SCL SDA VDD GND Description A-Side Source Terminal for Mux 1. Can be an input or output. B-Side Source Terminal for Mux 1. Can be an input or output. Drain Terminal for Mux 1. Can be an input or output. Drain Terminal for Mux 2. Can be an input or output. B-Side Source Terminal for Mux 2. Can be an input or output. A-Side Source Terminal for Mux 2. Can be an input or output. A-Side Source Terminal for Mux 3. Can be an input or output. B-Side Source Terminal for Mux 3. Can be an input or output. Drain Terminal for Mux 3. Can be an input or output. Drain Terminal for Mux 4. Can be an input or output. B-Side Source Terminal for Mux 4. Can be an input or output. A-Side Source Terminal for Mux 4. Can be an input or output. A-Side Source Terminal for Mux 5. Can be an input or output B-Side Source Terminal for Mux 5. Can be an input or output Drain Terminal for Mux 5. Can be an input or output. Not internally connected for ADG795A/General Purpose Logic Output 1 for ADG795G. Not internally connected. Logic Input. Sets Bit A2 from the least significant bit of the 7-bit slave address. Logic Input. Sets Bit A1 from the least significant bit of the 7-bit slave address. Logic Input. Sets Bit A0 from the least significant bit of the 7-bit slave address. Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into the device. External pull-up resistor required. Digital I/O. Bi-directional open-drain data line. External pull-up resistor required. Positive Power Supply Input. Ground (0 V) Reference.
Rev. 0 | Page 10 of 24
06034-003
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE TIED TO GND.
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE TIED TO GND.
S3A S3B D3 D4 S4B S4A
7 8 9 10 11 12
ADG795A/ADG795G TYPICAL PERFORMANCE CHARACTERISTICS
3.0 TA = 25C 1 CHANNEL VDD = 3.3V, RL = 1M VDD = 3V, RL = 1M
4.0 3.5 3.0 2.5
TA = 25C 1 CHANNEL
VDD = 5.0V VDD = 4.5V VDD = 5.5V
2.5
VDD = 2.7V, RL = 1M
OUTPUT SIGNAL (V)
2.0
VDD = 3.3V, RL = 75 VDD = 3V, RL = 75 VDD = 2.7V, RL = 75
RON ()
06034-005
1.5
2.0 1.5 1.0
1.0
0.5
0.5 0
0
INPUT SIGNAL (V)
VD (VS) (V)
Figure 5. Analog Signal Range, 3 V Supply
5.0 4.5 4.0
Figure 8. On Resistance vs. VD (VS), 5 V Supply
7
VDD = 5.5V, RL = 1M VDD = 5V, RL = 1M VDD = 5.5V, RL = 75 VDD = 4.5V, RL = 1M
TA = 25C 1 CHANNEL 6 VDD = 3V TA = +85C 5
OUTPUT SIGNAL (V)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 INPUT SIGNAL (V) 4 VDD = 5V, RL = 75 VDD = 4.5V, RL = 75
RON ()
4 TA = -40C 3 TA = +25C 2 1
TA = 25C 1 CHANNEL 5 6
06034-006
0
VD (VS) (V)
Figure 6. Analog Signal Range, 5 V Supply
6
Figure 9. On Resistance vs. VD (VS) for Various Temperatures, 3 V Supply
4.5
TA = 25C 1 CHANNEL VDD = 2.7V
VDD = 3.0V
4.0 3.5
5
TA = +25C 1 CHANNEL VDD = 5V
TA = +85C TA = +25C TA = -40C
4
VDD = 3.3V
3.0
RON ()
3
RON ()
2.5 2.0 1.5 1.0
2
1 0.5 0 0
06034-007
VD (VS) (V)
VD (VS) (V)
Figure 7. On Resistance vs. VD (VS), 3 V Supply
Figure 10. On Resistance vs. VD (VS) for Various Temperatures, 5 V Supply
Rev. 0 | Page 11 of 24
06034-010
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
0.5
1.0
1.5
2.0
2.5
3.0
06034-009
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
06034-008
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
ADG795A/ADG795G
0 -0.5 -1.0 TA = 25C VDD = 3V VDD = 5V
CROSSTALK (dB)
-40 SAME MULTIPLEXER 0 TA = 25C VDD = 3V/5V
-20
CHARGE INJECTION (pC)
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5
-60 DIFFERENT MULTIPLEXER
-80
-100
06034-011
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.1
1
10
100
1000
SOURCE VOLTAGE (V)
FREQUENCY (MHz)
Figure 11. Charge Injection vs. Source Voltage
220
Figure 14. Crosstalk vs. Frequency
-1
210
-3
TA = 25C VDD = 5V
tON (3V)
ATTENUATION (dB)
200
tON/tOFF (ns)
tOFF (3V)
-5 -7 -9 -11
190
180
tON (5V) tOFF (5V)
170
-13 -15 0.01
-20
0
20
40
60
80
06034-012
0.1
1
10
100
1000
TEMPERATURE (C)
FREQUENCY (MHz)
Figure 12. tON/tOFF vs. Temperature
0 0 TA = 25C VDD = 3V/5V
Figure 15. Bandwidth
TA = 25C -10 1 CHANNEL VDD = 3V/5V -20 NO DECOUPLING CAPACITORS USED -30
-20
OFF ISOLATION (dB)
-40
PSRR (dB)
-40 -50 -60 -70 -80
-60
-80
-100 -90 0.001 0.01 0.1 1 10 100 1000
06034-016
0.1
1
10
100
1000
06034-013
-120 0.01
-100 0.0001
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Off Isolation vs. Frequency
Figure 16. PSRR vs. Frequency
Rev. 0 | Page 12 of 24
06034-015
160 -40
06034-014
-5.0
-120 0.01
ADG795A/ADG795G
0.40 0.35 0.30
GPO VOLTAGE (V)
TA = 25C
6
TA = 25C
5 VDD = 5V VDD = 5V 4
0.25
IDD (mA)
0.20 0.15 VDD = 3V 0.10 0.05 0 0.1
3 VDD = 3V 2
1
06034-017
0.6
1.1
1.6
2.1
2.6
3.1
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
fCLK FREQUENCY (MHz)
LOAD CURRENT (mA)
Figure 17. IDD vs. fCLK Frequency
1.4 1.2 VDD = 5V 1.0 0.8
IDD (mA) GPO VOLTAGE (V)
Figure 20. GPO VOH vs. Load Current
2.5
TA = 25C 2.0
TA = 25C VDD = 3V VDD = 5V
1.5
0.6 0.4 0.2 0 VDD = 3V
1.0
0.5
0
1 I2C
2
3
4
5
6
06034-018
0
5
10
15
20
25
30
35
LOGIC INPUT VOLTAGE (V)
LOAD CURRENT (mA)
Figure 18. IDD vs. I2C Logic Input Voltage (SDA, SCL)
120
Figure 21. GPO VOL vs. Load Current
PROPAGATION DELAY (ns)
115
110
tPHL (5V) tPLH (5V)
tPHL (3V)
105
tPLH (3V)
100
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 19. I2C to GPO Propagation Delay vs. Temperature
06034-019
95 -40
Rev. 0 | Page 13 of 24
06034-021
-0.2
0
06034-020
0 -20
ADG795A/ADG795G TEST CIRCUITS
VDD
0.1F
IDS
V1 S VS D
SA
NETWORK ANALYZER 50 50 VS 50
SB
06034-022
RON = V1/IDS
D 50 GND
VOUT
Figure 22. On Resistance
Figure 25. Bandwidth
VDD
0.1F NETWORK ANALYZER S
06034-023
IS (OFF) A VS
S
D
ID (OFF) A VD
50 50 D 50
50 VS
VOUT 50
GND
06034-028
Figure 23. Off Leakage
VDD
Figure 26. Off Isolation
0.1F NETWORK ANALYZER
S D ID (ON) A VD NC = NO CONNECT
SX
50
50 VS
NC
06034-024
SY DY DX
50 VOUT RL 50
Figure 24. On Leakage
Figure 27. Channel-to-Channel Crosstalk
Rev. 0 | Page 14 of 24
06034-029
GND
50
50
06034-027
ADG795A/ADG795G
CLOCK PULSES CORRESPONDING TO THE LDSW BITS SCL 5V 50% 50%
0.1F VOUT VDD S VS I2C INTERFACE SCL SDA SCL D RL 50 VOUT CL 35pF
90% 10%
tON
CLOCK PULSES CORRESPONDING TO THE LDSW BITS 50% 50%
tOFF
GND VGPO
90% 10%
06034-025
tH
tL
Figure 28. Switching Times
5V CLOCK PULSE CORRESPONDING TO THE LDSW BIT VDD D RL 50 I2C INTERFACE VOUT CL 35pF VOUT VS 80% SCL
0.1F
SA VS SB
tD
GND
Figure 29. Break-Before-Make Time Delay
5V VDD RS VS GND S D CL 1nF VOUT SWITCH OFF QINJ = CL x VOUT
06034-030
SWITCH ON VOUT
Figure 30. Charge Injection
Rev. 0 | Page 15 of 24
06034-026
SDA
SCL
ADG795A/ADG795G TERMINOLOGY
On Resistance (RON) The series on-channel resistance measured between the S pin and D pin. On Resistance Match (RON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. On Resistance Flatness (RFLAT(ON)) The variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. Channel Off Leakage (IOFF) The sum of leakage currents into or out of an off channel input. Channel On Leakage (ION) The current loss/gain through an on-channel resistance, creating a voltage offset across the device. Input Leakage Current (IIN, IINL, IINH) The current flowing into a digital input when a specified low level or high level voltage is applied to that input. Input/Output Off Capacitance (COFF) The capacitance between an analog input and ground when the switch channel is off. Input/Output On Capacitance (CON) The capacitance between the inputs or outputs and ground when the switch channel is on. Digital Input Capacitance (CIN) The capacitance between a digital input and ground. Output On Switching Time (tON) The time required for the switch channel to close. The time is measured from 50% of the falling edge of the LDSW bit to the time the output reaches 90% of the final value. Output Off Switching Time (tOFF) The time required for the switch to open. The time is measured from 50% of the falling edge of the LDSW bit to the time the output reaches 10% of the final value. I2C to GPO propagation delay (tH, tL) The time required for the logic value at the GPO pin to settle after loading a GPO command. The time is measured from 50% of the falling edge of the LDSW bit to the time the output reaches 90% of the final value for high and 10% for low. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. -3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. Off Isolation The measure of unwanted signal coupling through an off switch. Crosstalk The measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Charge Injection The measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Differential Gain Error The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and expressed in percent (%). Differential Phase Error The measure of how much hue shift occurs when the luminance level changes. It can be a negative or positive value and is expressed in degrees of subcarrier phase. Input High Voltage (VINH) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum input voltage for Logic 0. Output High Voltage (VOH) The minimum output voltage for Logic 1. Output Low Voltage (VOL) The maximum output voltage for Logic 0. IDD Positive supply current.
Rev. 0 | Page 16 of 24
ADG795A/ADG795G THEORY OF OPERATION
The ADG795A/ADG795G are monolithic CMOS devices comprising five 2:1 multiplexers controllable via a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet offers high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG795A/ADG795G an ideal switching solution for a wide range of TV applications. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The integrated serial I2C interface controls the operation of the switches (ADG795A/ADG795G) and general-purpose logic pins (ADG795G only). The ADG795A/ADG795G have many attractive features, such as the ability to individually control each multiplexer, the option of reading back the status of any switch. The ADG795G has one general-purpose logic output pin controllable through the I2C interface. The following sections describe these features in detail. 3. Data transmits over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL. Otherwise, a low-to-high transition when the clock signal is high can be interpreted as a stop event that ends the communication between the master and the addressed slave device. After transferring all data bytes, the master establishes a stop condition, defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition.
4.
I2C ADDRESS
The ADG795A/ADG795G have a 7-bit I2C address. The four most significant bits are internally hardwired and last three bits (A0, A1, and A2) are user-adjustable. This allows the user to connect up to eight ADG795As/ADG795Gs to the same bus. The I2C bit map shows the configuration of the 7-bit address.
I2C SERIAL INTERFACE
The ADG795A/ADG795G are controlled via an I2C-compatible serial bus interface (refer to the I2C-Bus Specification available from Philips Semiconductor) that allows the part to operate as a slave device (no clock is generated by the ADG795A/ADG795G). The communication protocol between the I2C master and the device operates as follows: 1. The master initiates data transfer by establishing a start condition (defined as a high-to-low transition on the SDA line while SCL is high). This indicates that an address/data stream follows. All slave devices connected to the bus respond to the start condition and shift in the next eight bits, consisting of a seven bit address (MSB first) plus an R/W bit. This bit determines the direction of the data flow during the communication between the master and the addressed slave device. The slave device whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device.
7-Bit I2C Address Configuration
MSB 1 0 1 0 A2 A1 LSB A0
WRITE OPERATION
When writing to the ADG795A/ADG795G, the user must begin with an address byte and R/W bit, after which time the switch acknowledges that it is prepared to receive data by pulling SDA low. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. Figure 31 illustrates the entire write sequence for the ADG795A/ ADG795G. The first data byte (AX7 to AX0) controls the status of the switches while the LDSW and RESETB bits from the second byte control the operation mode of the device. Table 6 shows a list of all commands supported by the ADG795A/ ADG795G with the corresponding byte that needs to be loaded during a write operation. To achieve the desired configuration, one or more commands can be loaded into the device. Any combination of the commands in Table 6 can be used with these restrictions: * * Only one switch from a given multiplexer can be on at any given time. When a sequence of successive commands affect the same element (that is, the switch or GPO pin), only the last command is executed.
2.
Rev. 0 | Page 17 of 24
ADG795A/ADG795G
SCL SDA START CONDITION BY MASTER ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH A2 A1 A0 R/W AX7 AX6 AX5 AX4 AX3 AX2 AX1 AX0 X X X X X X RESETB LDSW
STOP CONDITION BY MASTER
06034-031
ACKNOWLEDGE BY SWITCH
Figure 31. Write Operation
Table 6. ADG795A/ADG795G Command List
AX7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 X1 X1 X1 X1 X1 X1 X1 1 0 0 1
1
AX6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
AX3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1
AX2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
AX1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AX0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1
Addressed Switch S1A/D1, S2A/D2, S3A/D3, S4A/D4, S5A/D5 off S1A/D1, S2A/D2, S3A/D3, S4A/D4, S5A/D5 on S1B/D1, S2B/D2, S3B/D3, S4B/D4, S5B/D5 off S1B/D1, S2B/D2, S3B/D3, S4B/D4, S5B/D5 on S1A/D1 off S1A/D1 on S1B/D1 off S1B/D1 on S2A/D2 off S2A/D2 on S2B/D2 off S2B/D2 on S3A/D3 off S3A/D3 on S3B/D3 off S3B/D3 on S4A/D4 off S4A/D4 on S4B/D4 off S4B/D4 on S5A/D5 off S5A/D5 on S5B/D5 off S5B/D5 on Reserved Reserved Mux 1 disabled (all switches connected to D1 are off ) Mux 2 disabled (all switches connected to D2 are off ) Mux 3 disabled (all switches connected to D3 are off ) Mux 4 disabled (all switches connected to D4 are off ) Mux 5 disabled (all switches connected to D5 are off ) Reserved GPO1 high for ADG795G/reserved for ADG795A GPO1 low for ADG795G/reserved for ADG795A All muxes disabled Reserved
X = Logic state does not matter.
Rev. 0 | Page 18 of 24
ADG795A/ADG795G
LDSW BIT
The LDSW bit allows the user to control the way the device executes the commands loaded during the write operations. The ADG795A/ADG795G execute all the commands loaded between two successive write operations that have set the LDSW bit high. Setting the LDSW high for every write cycle ensures that the device executes the command right after the LDSW bit was loaded into the device. This setting can be used when the desired configuration can be achieved by sending a single command or when the switches and/or GPO pin are not required to be updated at the same time. When the desired configuration requires multiple commands with simultaneous updated, the LDSW bit should be set low while loading the commands (except the last one when the LDSW bit should be set high). Once the last command with LDSW = high is loaded, the device executes all commands received since the last update simultaneously.
READ OPERATION
When reading data back from the ADG795A/ADG795G, the user must begin with an address byte and R/W bit. The switch then acknowledges that it is prepared to transmit data by pulling SDA low. Following this acknowledgement, the ADG795A/ADG795G transmit two bytes on the next clock edges. These bytes contain the status of the switches, and each byte is followed by an acknowledge bit. A logic high bit represents a switch in the on (close) state while a low represents a switch in the off (open) state. For the GPO pin (ADG795G only), the bit represents the logic value of the pin. Figure 32 illustrates the entire read sequence. The bit maps accompanying Figure 32 show the relationship between the elements of the ADG795A and ADG795G (that it, the switches and GPO pins) and the bits that represent their status after a completed read operation.
POWER ON/SOFTWARE RESET
The ADG795A/ADG795G has a software reset function implemented by the RESETB bit from the second data byte written to the device. For normal operation of the multiplexers and GPO pin, this bit should be set high. When RESETB = low or after power-up, the switches from all multiplexers are turned off (open) and the GPO pin is set low.
Bit Map of the ADG795A
RB15 S1A/D1 RB14 S1B/D1 RB13 S2A/D2 RB12 S2B/D2 RB11 S3A/D3 RB10 S3B/D3 RB9 S4A/D4 RB8 S4B/D4 RB7 S5A/D5 RB6 S5B/D5 RB5 RB4 RB3 RB2 RB1 RB0 -
Bit Map of the ADG795G
RB15 S1A/D1 RB14 S1B/D1 RB13 S2A/D2 RB12 S2B/D2 RB11 S3A/D3 RB10 S3B/D3 RB9 S4A/D4 RB8 S4B/D4 RB7 S5A/D5 RB6 S5B/D5 RB5 RB4 RB3 GPO1 RB2 RB1 RB0 -
Read Operation
SCL A2 ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH A1 A0 R/W RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
SDA START CONDITION BY MASTER
ACKNOWLEDGE BY SWITCH
Figure 32. ADG795A/ADG795G Read Operation
Rev. 0 | Page 19 of 24
06034-032
STOP CONDITION BY MASTER
ADG795A/ADG795G EVALUATION BOARD
The ADG795G evaluation kit allows designers to evaluate the high performance of the device with a minimum of effort. The evaluation kit includes a printed circuit board populated with the ADG795G. The evaluation board can be used to evaluate the performance of both the ADG795A and ADG795G. It interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. Software for the evaluation board allows the user to program the ADG795G easily through the USB port. The software runs on any PC that has Microsoft(R) Windows(R) 2000 or Windows XP installed with a minimum screen resolution of 1200 x 768. See Figure 33 and Figure 34 for schematics of the evaluation board.
USING THE ADG795G EVALUATION BOARD
The ADG795G evaluation kit is a test system designed to simplify the evaluation of the device. Each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. An evaluation board data sheet is also available and provides full instructions for operating the evaluation board.
Rev. 0 | Page 20 of 24
3.3V 3.3V T1 3.3V 3.3V 24LC64
8
C22 0.1F R1 2.2k R2 2.2k
J2-1 3.3V R7 0
J2-2
R5 75 C18 0.1F U2
3 7 11 17 27 32 43 55
R6 75 C23 2.2F 3.3V VCC 7 WP 6 SCL 5 VSS SDA
1 A0 2 A1 3 A2 4
T4
C4 10F
C9 0.1F
AVCC VCC VCC VCC VCC VCC VCC VCC
42
3.3V SCL_EN R12 2.2k G S Q1 D G T27 T28 S U4
1 2
VDD R9 2.2k
J1 USB-MINI-B
44 1 2 9 8 3 4 5 54
VBUS D- D+ IO GND *DENOTES PROGRAMMABLE POLARITY.
16 15 4 5
SHIELD
R31 10k
R32 10k
SDA
33 34 35 36 37 38 39 40 1 2 13 14
18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 29 30 31
Q2
D
SCL
R10 10k
10 12 26 28 41 53 56
VDD
6
C6 0.1F C8 0.1F C20 0.1F
AGND
GND GND GND GND GND GND GND
06034-033
Figure 33. Eval-ADG795GEB Schematic, USB Controller Section
3.3V
ADG821
S1 D1
3
3.3V VDD IN1 IN2 XTAL1 24MHz
4 8 7
Rev. 0 | Page 21 of 24
C5 0.1F C19 0.1F C21 0.1F C7 0.1F C17 22pF B T26 3.3V
C2 0.1F SCL_EN D2 GND C10 22pF S2
6 5
PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 RESET PB4/FD4 *WAKEUP PB5/FD5 PB6/FD6 CLKOUT PB7/FD7 U3 PD0/FD8 CY7C68013-CS P PD1/FD9 D- PD2/FD10 PD3/FD11 D+ PD4/FD12 PA0/INT0 PD5/FD13 PA1/INT1 PD6/FD14 PA2/*SLOE PD7/FD15 PA3/*WU2 CTL0/*FLAGA PA4/FIFOADR0 CTL1/*FLAGB PA5/FIFOADR1 PA6/*PKTEND CTL2/*FLAGC PA7/*FLD/SLCS SDA RDY0/*SLRD SCL RDY1/*SLWR IFCLK XTALOUT RSVD XTALIN
J5
A
ADP3303-3.3
8 7 IN2 5
IN1 C14 10F C16 0.1F
1
C13 10F
C3 0.1F
OUT1 2 OUT2 6 SD ERROR 3 GND NR 4 U5
C15 0.1F
R11 1k D4
ADG795A/ADG795G
3.3V
1 4 5
K7
T15 T14 T13 T12 T11 T10
GND 2 BOTTOM 3 CASE TOP CASE
R25
PHONO_DUAL R26
T18
1 4 5
K8 R27
GND 2 BOTTOM 3 CASE TOP CASE
PHONO_DUAL
R28
T20
T22 T23
PADDLE
1 4 5
K9 GND 2 BOTTOM 3 CASE TOP CASE R29
GPO1
R36 0
PHONO_DUAL R30
06033-034
ADG795A/ADG795G
Figure 34. Eval-ADG795GEB Schematic, Chip Section
Rev. 0 | Page 22 of 24
4 1 1 4 1
K6
K5
K4
PHONO_DUAL
PHONO_DUAL
PHONO_DUAL
GND 2 BOTTOM 3 CASE TOP 5 CASE
GND 2 BOTTOM 4 3 CASE TOP 5 CASE
GND 2 BOTTOM 3 CASE TOP 5 CASE
GPO2 R24 T16 T17 T19 T21 SDA SCL
R23 A
12 11 10 9 8 7 25
R22
R21 T2 T3
R20
R19
R13
PHONO_DUAL
5
2
CASE 3 TOP 4 CASE BOTTOM 1 GND R14 K3
R15
PHONO_DUAL
5
6 5 4 3 2 1
13 14 15 16 17 18
ADG795G
2
R34 0 R35 0
A
CASE 3 TOP 4 CASE BOTTOM 1 GND K2
R3 10k
R4 10k
R8 10k
U1
19 20 21 22 23 24
R16 R17
PHONO_DUAL
5
T24
2
T7 T25 T8 T9
CASE 3 TOP 4 CASE BOTTOM 1 GND K1 R18
J3
J7
J8
GPO2
GPO1
T5 T6 J6-3 J6-2 J6-1 SCL
SDA
C1 0.1F VDD
J4-2
J4-3
J4-1
SCL SDA
ADG795A/ADG795G OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP
19 18 EXPOSED PAD 24 1
PIN 1 INDICATOR *2.45 2.30 SQ 2.15
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
(BO TTOMVIEW)
13 12
7
0.23 MIN 2.50 REF
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG795ABCPZ-REEL 1 ADG795ABCPZ-500RL71 ADG795ACCPZ-REEL1 ADG795ACCPZ-500RL71 ADG795GBCPZ-REEL1 ADG795GBCPZ-500RL71 ADG795GCCPZ-REEL1 ADG795GCCPZ-500RL71 EVAL-ADG795GEB 2
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
I2C Speed 100 kHz, 400 kHz 100 kHz, 400 kHz 100 kHz, 400 kHz, 3.4 MHz 100 kHz, 400 kHz, 3.4 MHz 100 kHz, 400 kHz 100 kHz, 400 kHz 100 kHz, 400 kHz, 3.4 MHz 100 kHz, 400 kHz, 3.4 MHz
Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Evaluation Board
Package Option CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2
Z = Pb-free part. Evaluation board is RoHS compliant.
Rev. 0 | Page 23 of 24
ADG795A/ADG795G NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06034-0-7/06(0)
Rev. 0 | Page 24 of 24

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